Anupc
(Anup)
September 5, 2026, 9:34pm
34
Simon2:
The answer from dCS was troubling. Simply put, dCS’s argument is that their internal jitter processing requires an accurate input, and the allowance for jitter error is not wide enough for some TV optical output signals.
The key answer to why dCS won’t “relax” it’s jitter threshold for just the TOSLink interface is in the last line of Andrew’s recent post in the Transport thread;
What he said. In this case all products would be operating in the same clock domain.
Just to point out however that our clocking architecture has two main components, the clock signal from the master clock, its jitter and accuracy characteristics, and the PLL that connects it to the clock(s) in the DAC(s) and source component(s). These are every bit as important as the quality of the clock signal itself.
In my flywheel analogy, if the master clock is the flywheel that stabilizes the rotatio…