What he said. In this case all products would be operating in the same clock domain.
Just to point out however that our clocking architecture has two main components, the clock signal from the master clock, its jitter and accuracy characteristics, and the PLL that connects it to the clock(s) in the DAC(s) and source component(s). These are every bit as important as the quality of the clock signal itself.
In my flywheel analogy, if the master clock is the flywheel that stabilizes the rotational speed of the driven wheel, the PLL is the belt that connects them together. If the belt is stretchy or uneven, it doesn’t matter how accurate the rotational speed of the flywheel is, that accuracy won’t be conveyed to the driven wheel and it might actually make things worse.
Our PLLs are developed by us and implemented in FPGA code. We don’t use off-the shelf PLL chips. They are a core part of our clocking architecture.