At the PHYsical layer, Ethernet is similar to S/PDIF in that it’s a serial digital bitstream that carries both data and associated clock. And just like S/PDIF, the Ethernet PHY Transceiver at the receiving-end typically synchronises to the incoming bitstream via Phase Locked Loops (PLL) and extracts the associated data.
However, unlike S/PDIF which is a continuous synchronous bitstream with no mechanism for correction, Ethernet is bursty self-contained frames with an 8-byte preamble at the start of each frame designed to (a) wake-up the receiver, (b) re-synchronise the receiver to the incoming bitstream, and (c) signify the start of the Ethernet frame. While at the end of each Ethernet frame is a 4-byte error-check sequence which the receiver uses to detect transmission errors and discard errored frames in order for the upper layers to request the data to be resent.
I highly recommend slowly re-reading James’ pieces on Clocking, start here;