Come on, there has to be a technical disadvantage. Being an engineer, there are always compromises. Nothing comes free. I’m sure the filter isn’t perfect removing the dithering completely, and probably moves the noise to a different part of the spectrum. If I wasn’t so incredibly busy right now, I’d figure it out myself. 
I have all winter…
Yes but its audibility is open to question. I am unable to hear any difference and thus express any preference either way. However I maintain it on a belt and braces principle. ( not sure the American English version).
From distant recollection it was introduced in a later series of dCS clocks to ameliorate a potential “dead spot” ( in the PLL ?? - I am very vague).. It wasn’t in earlier dCS closks and I was never aware of it’s absence.
Unsure whether noise is moved however.
Pete, you’re right that Dither wasn’t a capability in the 992, but it first appeared in the Verona Master Clock. There was even a 3-page dCS Clocking White Paper that touched on this Dither capability (in 2004).
IINM, every dCS Clock since then has had Dither capability. Except until the Lina Clock and now the Varèse Clock, both which don’t have it.
So I went back to the well on this and asked Chris, please find his response below. In summary it wasn’t so much about advantages/disadvantages as different potential use cases.
Dither is most useful when the PLL locking to the clock suffers a dead band with its phase detector. As a PLL gets closer into lock the output from the phase detector gets narrower and narrower and there is a range of lock alignments where the output of the phase detector is effectively zero. Whilst the PLL is within this range it is effectively coasting and will continue to do so until either one of the clocks has changed enough to bring the phase detector back into its active range or natural drift within the loop has done the same. As a result, the PLL tends to “hunt” around the lock point with characteristics determined by the ballistics of the loop and the specific behaviour of the phase detector. Under these circumstances, dithering the clock can be beneficial in that the phase detector never enters this dead zone and so the characteristics of the lock behaviour are determined by the dithered clock rather than the peculiarities of the PLL. My angle has always been, therefore, that lesser PLLs than dCS’ may benefit from this whilst a well-behaved PLL** doesn’t. This, of course, is somewhat contradicted by the observations of some of our customers that our products do also benefit sonically from having dither applied to the clock.
** AS Note: remember that we implement our own PLLs in FPGA code so control every aspect of their operation. The vast majority of DACs use the PLLs embedded in S/PDIF receiver chips.
So if I’m reading the response from Chris correctly, the dither function is not required for dCS dacs
Yes, that’s my read too.
Perhaps that the reason why i cannot tell any difference between it switched on or off. Makes me wonder about those who say they can though.