[FAQ] How does the Dither feature on dCS Master Clocks work?

With a Master Clock in the system, the Transport, Upsampler and DAC use their internal Phase Locked Loop (PLL) circuits to lock to the Master Clock. PLLs use a phase detector to determine the frequency difference between the incoming clock and the internal clock, then adjust the internal clock slightly so that the two clocks are at the same frequency – locked. Unfortunately, phase detectors are not very sensitive to the very small frequency errors found near the lock point.

The Dither feature modulates the edges in a very controlled way, causing brief phase errors that give the PLL something to work with. Short-term, this means that tiny errors are corrected more accurately by avoiding the dead zone. Medium term, the modulation averages out, it is filtered out by the PLL and does not affect the Clock accuracy at all. It might seem crazy, but it works!

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