So what I understand is using external clock in this case essentially helps with is avoiding the intrinsic Jitter of the internal clock. The external clock being a separate single purpose built unit with smaller power supply, better clock material, temperature control, etc ismore stable and intrinsic jitter free. Right ?
Recently, 3rd party organizations are keen on measurements of the gears, such as DACs, AMPs,Digital transports, etc, which aims to measure the specifications,for instance, SINAD,THD+N, Dynamic Range, Linearityļ¼12Kļ¼Multitoneļ¼etc. Some gearsā tests are awesome, while actual subjective feelings are not good ,can you say something about it
Few Qs related to upsampling involving Rossini Transport and Rossini Dac (just got them delivered 3 days back - enjoying all kind of experimentation with sound !!!)
If I integrate Rossini Transport with Rossini Dac using dual AES, will Dacās upsampling be no longer used as Transport is anyway upsampling the data ?
When a DSD64 data stream is upsampled to DSD128 (in either of these 2 boxes) does the upsampling logic first filter out the above 20 Khz ultrasonic noise present in the original stream before upsampling ?
Is the point 2 also applicable for PCM data upsampled to DSD128 ?
I understand the DSD filter 4 is primarily for testing purpose. But for some old recordings (not good recordings) I am finding that filter 4 with DSD upsampling at least makes the music listenable without any harshness. But do u think use of filter 5 (which ensures roll off than sharp cut off of above 25 khz frequencies) with DSD128 upsampling should give better result (removal of harshness) for majority of the bad recordings.
Iām really glad to hear you are enjoying your new Rossini system!
Yes and no. The Upsampling setting in the Rossini DAC dictates if the optional DSD stage is added in during the PCM Oversamplnig process, or if the unit carries out standard PCM Oversampling.
This Oversampling process always has to happen, eventually feeding the Ring DAC with the high-rate 5-bit signal.
If you increase the sample rate of the incoming signal, such as to 24/352.8kS/s (the DXD Upsampling setting on the Rossini Transport), the DAC will no longer need to carry out this part of the process as the Transport has already taken care of it. Instead, it just works to Oversample this signal up to the high rate Ring DAC format.
Incoming DSD data to the Rossini is not changed by the Upsampling setting. This setting adds an optional DSD or DSD2 Upsampling phase in to the end of the PCM Oversampling process, so has no impact on DSD data.
The noise inherent in DSD/128 is naturally scaled up when compared to DSD/64 data, so the filter does not need to come in until around 40kHz. No need to filter it twice.
I would personally expect filter 5 to provide better performance - filter 4 is unusually steep for actual listening purposes, and is really in place to test, for example, systems which are particularly sensitive or vulnerable to the inherent noise with DSD. Filter 5 should typically provide better audible results.
A followup/further clarification on point 1 - If the transport is sending 24/352.8 and in Dac I have set upsampling to DSD128, in that case dac will add only the DSD stage to the incoming data. Right ? Or as because it does not need to do standard PCM upsampling it will not add the DSD stage ?
Would it be possible to improve the R2R by measuring the actual resistance of each resistor in the ladder and then adjusting for the error in the sum with a DAC specific FPGA algorithm? Since the amount of error in each resistor is fixed it seems that it could be accounted for in each DAC instance to reduce this potential linear distortion.
Yes, it is possible to have a calibration mechanism that compensates for resistor errors in an R-2R design. If done correctly it can yield good results initially. The difficulty here is that naturally some of the current sources in the DAC will be turned on/off more than others given that a current source is correlated to a particular bit in the digital audio word, which in turn causes uneven aging of (among other things) the resistors in the current sources. This will cause the resistance to drift out from the original compensation over time, with linear distortion occurring as a result.
If you are operating the Ring DAC correctly (or any thermometer DAC for that matter), over time all of the current sources (and therefore the resistors) will be used the same amount. They will therefore age in a uniform way. We do account for resistors aging in the Ring DAC on the software side, made possible by the uniform aging of components.
Thank you sir for your thorough reply. This makes a ton of sense to me. I intend to acquire one of your Ring DACs when I have the opportunity. Thank you again for taking the time to reply here. Your posts have been extremely informative.
Is this a PID sort of control algorithm built into the FPGA? If so, are the tuning constants self-learning to optimize for local environmental operating conditions as compared to the chamber, in order to minimize over and under correction?
In order to maintain SNR this seems to imply that after the SNR gain of oversampling, the delta sigma modulator employed is somewhere between 3rd and 7th order and which order modulator actually used is selected in the mapper based on the incoming file frequency and bit depth. Would this be an accurate assumption?
That is an interesting question, because it must be difficult for a designer to make the decision between sharing information and keeping industrial secretā¦we see the answer of dCS or not
I think Iām still at a very basic level so no proprietary secret being asked to be divulged, but if so, I would certainly respect that reply. Iām really asking as a means to validate I am understanding what they published in their white paper on the Ring DAC. Since the SNR of 5 bit is so much lower than 16 to 24 bit PCM, Iām trying to account for the difference, given that the frequency after oversampling stage is only doubling two to three times.
