@James
thanks a lot for the first PDF. I am looking forward to the other ones.
Could you please look at the quality of the diagrams? They seem unsharp, much less sharp than the text.
One thing I missed out here.
If for tcp based n/w interface/source the timing information from original source is anyway lost because of buffering etc, then how using an external clock (instead of Dac’s internal clock) can address that issue ?
Regards,
Sourav
Timing is not lost from any original source as it is in fact always imbedded within each PCM sample during the A-to-D stage. The physical media, such as a CD, is not where the original music source timing information is retained.
Once the TCP streams are decapsulated as PCM samples within the dCS platform, they’re synchronously clocked out precisely, exactly the same as all other (synchronous) inputs, and processed through to the final D-to-A conversion.
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Well I made the comment based on this statement “This stage, the unpacking and buffering, effectively removes any timing link between the TCP packets and the resultant audio signal. (Read that sentence again, as it’s very important.)” which is applicable for N/W and Asynch USB sources.
Regards,
Sourav
That timing James is referring to is the timing associated with the reception of IP packet, from across the Internet, or even from a Compute platform over USB; Packets arrive in bursts and with a lot of jitter. The buffers within the dCS’ network board ensures that those bursts/jitter have zero impact on the quality of audio playback.
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In this case, as Anup has explained below, there is no timing link between the source material and the DAC. The DAC does not have any other clock domains to worry about here, so it simply converts the audio samples from it’s buffer at it’s own rate. If there is a Master Clock in the system, this means that the DAC then has a cleaner external reference clock signal to lock to, ensuring the timing of when these samples are converted is good and reliable.
Using a Master Clock in this case does not solve any problems, but it does increase audio quality (see the Intrinsic Jitter post for details on how).
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@James @Anupc thanks for the detailed inputs.
So what I understand is using external clock in this case essentially helps with is avoiding the intrinsic Jitter of the internal clock. The external clock being a separate single purpose built unit with smaller power supply, better clock material, temperature control, etc ismore stable and intrinsic jitter free. Right ?
Regards,
Sourav
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Yes, that is absolutely correct.
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Hi, James
Recently, 3rd party organizations are keen on measurements of the gears, such as DACs, AMPs,Digital transports, etc, which aims to measure the specifications,for instance, SINAD,THD+N, Dynamic Range, Linearity，12K，Multitone，etc. Some gears’ tests are awesome, while actual subjective feelings are not good ,can you say something about it
HI James,
Few Qs related to upsampling involving Rossini Transport and Rossini Dac (just got them delivered 3 days back - enjoying all kind of experimentation with sound !!!)
- If I integrate Rossini Transport with Rossini Dac using dual AES, will Dac’s upsampling be no longer used as Transport is anyway upsampling the data ?
- When a DSD64 data stream is upsampled to DSD128 (in either of these 2 boxes) does the upsampling logic first filter out the above 20 Khz ultrasonic noise present in the original stream before upsampling ?
- Is the point 2 also applicable for PCM data upsampled to DSD128 ?
- I understand the DSD filter 4 is primarily for testing purpose. But for some old recordings (not good recordings) I am finding that filter 4 with DSD upsampling at least makes the music listenable without any harshness. But do u think use of filter 5 (which ensures roll off than sharp cut off of above 25 khz frequencies) with DSD128 upsampling should give better result (removal of harshness) for majority of the bad recordings.
Regards,
Sourav
Hi Sourav,
I’m really glad to hear you are enjoying your new Rossini system!
- Yes and no. The Upsampling setting in the Rossini DAC dictates if the optional DSD stage is added in during the PCM Oversamplnig process, or if the unit carries out standard PCM Oversampling.
This Oversampling process always has to happen, eventually feeding the Ring DAC with the high-rate 5-bit signal.
If you increase the sample rate of the incoming signal, such as to 24/352.8kS/s (the DXD Upsampling setting on the Rossini Transport), the DAC will no longer need to carry out this part of the process as the Transport has already taken care of it. Instead, it just works to Oversample this signal up to the high rate Ring DAC format. - Incoming DSD data to the Rossini is not changed by the Upsampling setting. This setting adds an optional DSD or DSD2 Upsampling phase in to the end of the PCM Oversampling process, so has no impact on DSD data.
- The noise inherent in DSD/128 is naturally scaled up when compared to DSD/64 data, so the filter does not need to come in until around 40kHz. No need to filter it twice.
- I would personally expect filter 5 to provide better performance - filter 4 is unusually steep for actual listening purposes, and is really in place to test, for example, systems which are particularly sensitive or vulnerable to the inherent noise with DSD. Filter 5 should typically provide better audible results.
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Thanks for the detailed response.
A followup/further clarification on point 1 - If the transport is sending 24/352.8 and in Dac I have set upsampling to DSD128, in that case dac will add only the DSD stage to the incoming data. Right ? Or as because it does not need to do standard PCM upsampling it will not add the DSD stage ?
Regards,
Sourav
Would it be possible to improve the R2R by measuring the actual resistance of each resistor in the ladder and then adjusting for the error in the sum with a DAC specific FPGA algorithm? Since the amount of error in each resistor is fixed it seems that it could be accounted for in each DAC instance to reduce this potential linear distortion.
Hi Kevin,
Yes, it is possible to have a calibration mechanism that compensates for resistor errors in an R-2R design. If done correctly it can yield good results initially. The difficulty here is that naturally some of the current sources in the DAC will be turned on/off more than others given that a current source is correlated to a particular bit in the digital audio word, which in turn causes uneven aging of (among other things) the resistors in the current sources. This will cause the resistance to drift out from the original compensation over time, with linear distortion occurring as a result.
If you are operating the Ring DAC correctly (or any thermometer DAC for that matter), over time all of the current sources (and therefore the resistors) will be used the same amount. They will therefore age in a uniform way. We do account for resistors aging in the Ring DAC on the software side, made possible by the uniform aging of components.
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Thank you sir for your thorough reply. This makes a ton of sense to me. I intend to acquire one of your Ring DACs when I have the opportunity. Thank you again for taking the time to reply here. Your posts have been extremely informative.
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Is this a PID sort of control algorithm built into the FPGA? If so, are the tuning constants self-learning to optimize for local environmental operating conditions as compared to the chamber, in order to minimize over and under correction?
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In order to maintain SNR this seems to imply that after the SNR gain of oversampling, the delta sigma modulator employed is somewhere between 3rd and 7th order and which order modulator actually used is selected in the mapper based on the incoming file frequency and bit depth. Would this be an accurate assumption?
That is an interesting question, because it must be difficult for a designer to make the decision between sharing information and keeping industrial secret…we see the answer of dCS or not 
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I think I’m still at a very basic level so no proprietary secret being asked to be divulged, but if so, I would certainly respect that reply. I’m really asking as a means to validate I am understanding what they published in their white paper on the Ring DAC. Since the SNR of 5 bit is so much lower than 16 to 24 bit PCM, I’m trying to account for the difference, given that the frequency after oversampling stage is only doubling two to three times.
Interesting:
Seems dCS was ahead of the game on obtaining quantum computing results…