Clock cables matter more where?

[Anupc (Anup)]

Actually, when an external clock/cable is used, it’s only as a reference signal used to fine-tune the internal clock of the DAC (which is then used for D-to-A conversion) via a PLL stage on the Control Board FPGA.

That PLL stage in fact acts as a low-pass-filter that eliminates jitter from the incoming external clock signal/cable before it’s used as a reference for the DAC’s internal clock.

So, any minute amounts of jitter caused by the cable, has no real consequence in the overall scheme of things.

James explains this clearly in his Technical Explanation posts, specifically post #51

dCS Ring DAC - A Technical Explanation

Part 4 – Clock Synchronisation There is a problem posed when multiple digital audio devices, each with their own internal clocks, need to work together. Take the example of feeding a CD transport into a DAC. The DAC has a buffer – a section of temporary memory which stores the audio samples it receives from the CD transport. The transport’s clock dictates when a sample is sent out to the DAC, and the DAC’s clock dictates when the sample is used and converted to an analogue voltage. In an ideal…

Also, the following two videos from Silicon Labs describes clock jitter and PLLs quite well (@2:40 in Part 2 explains jitter elimination with the PLL);

Part 1: Clock Jitter, Jitter Classifications and Measurements

Part 2: Jitter Characteristics as Applied to PLLs and Clock Buffers